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Puma devices for XENPAK, X2 and XPAK applications
The Puma family of devices is a single channel, CMOS, 10-Gbps serial to 4-lane XAUI SerDes portfolio, designed for use in optical modules and LAN/WAN/MAN/SAN PHY system applications.
Puma AEL1001
XAUI/10G LAN PHY SerDes |
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FEATURES
- 10GbE & 10G Fibre Channel PHY/SerDes (10 Gbps-to-XAUI) for XENPAK, X2 & XPAK optical modules
- 800 mW power consumption
- Integrated limiting amplifier
- Multiple loop-back modes
- Full support for XENPAK, IEEE, and customer-specific register requirements
- Pin compatible with AEL1004/AEL1006
- Built-in PRBS & BER Features
- MDIO, JTAG & SDA/SCL physical interfaces
- Adjustable XAUI transmit pre-emphasis for 40 inches of FR4 with 1 connector
- Programmable bit & lane ordering
Puma AEL1003
XAUI/10G LAN/WAN PHY SerDes + EDC |
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FEATURES
- 10GbE PHY/SerDes (10 Gbps-to-XAUI) with integrated EDC for 10GBASE-LRM
- Integrated adaptive equalization based on FFE/DFE implementation - equalizes pre-cursor, post-cursor & symmetric pulses (IEEE 802.3aq)
- Lowest power consumption of 1.4W (PHY + EDC)
- Multiple loop-back modes
- Packet, PRBS, CJPAT & CRPAT generators & checkers
- MDIO, JTAG & SDA/SCL physical interfaces
- Smallest package size (10mm x 10mm)
- Full support for XENPAK, IEEE, and customer-specific register requirements
- Adjustable XAUI transmit pre-emphasis for 40 inches of FR4 with 1 connector
- Programmable bit & lane ordering
Puma AEL1004
XAUI/10G LAN/WAN PHY SerDes |
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FEATURES
- 10GbE PHY/SerDes (10 Gbps-to-XAUI) for XENPAK, X2 & XPAK optical modules
- Integrated WAN Interface Sublayer (WIS) IEEE 802.3ae Clause 50-compliant
- Integrated clock synthesizers allows 156.25MHz to be synthesized from a 155.52MHz input (optional 50 MHz input)
- SONET-quality jitter performance
- Multiple loop-back modes
- Full support for XENPAK, IEEE, and customer-specific register requirements
- Pin compatible with AEL1001/1006
- MDIO, JTAG & SDA/SCL physical interfaces
- Built-in PRBS & BER Features
- Adjustable XAUI transmit pre-emphasis for 40 inches of FR4 with 1 connector
- Programmable bit & lane ordering
Puma AEL1006
10G LAN PHY/SerDes with VCSEL driver |
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FEATURES
- 10GbE & 10G Fibre Channel PHY/SerDes (10 Gbps-to-XAUI) for XENPAK, X2 & XPAK optical modules
- Integrated 850nm VCSEL driver implemented
- On-chip clock synthesizer allows 156.25MHz to be synthesized from a 50 MHz input
- Pin compatible with AEL1001/1004
- Multiple loop-back modes
- Full support for XENPAK, IEEE, and customer-specific register requirements
- MDIO, JTAG & SDA/SCL physical interfaces
- Built-in PRBS & BER Features
- Adjustable XAUI transmit pre-emphasis for 40 inches of FR4 with 1 connector
- Programmable bit & lane ordering
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Benefits
- Industry’s lowest power consumption
- Optimized for XAUI-based optical modules (XENPAK, X2 and XPAK)
- Smallest size (13x13 mm)
- Meets all XAUI and 10G jitter specs, XENPAK specs
- XAUI pre-emphasis for extended distances (up to 40 in of FR4)
- Quality & reliability built in (well-established packaging technology, generic processing technology, reliability monitoring program)
- Fully qualified and shipping to end-customers
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