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By leveraging the team’s background in mixed signal designs, Aeluros has not only been the first to develop a 10GbE PHY/SerDes device with <1W power consumption, but remains the leader today in the low power 10G PHY devices.
Aeluros’s Puma devices are fabricated in 0.13 micron CMOS technology and use standard PBGA packaging technology. Both these technologies are in full production today and have matured to the point where no special features, options or materials are required to fabricate the Puma family of products.
Aeluros has also completed extensive quality and reliability testing on its devices. In some cases, these tests have been performed in excess of standard requirements (example, 4000 hours of HTOL)
More details on Aeluros’ technology approach can be viewed at:
An 800mW 10-Gigabit Ethernet Transceiver in 0.13um CMOS
IEEE International Solid-State Circuits Conference (ISSCC) 2004, February 17, 2004
Package and Test Environment Design for a 10 Gigabit Ethernet Transceiver
DesignCon 2004, February 3, 2004
Error-Correction Coding for 10 Gbps Backplane Transmission
DesignCon 2004, February 3, 2004
An Integrated VCSEL Driver for 10Gb Ethernet CMOS
IEEE International Solid-State Circuits Conference (ISSCC) 2004, February 7, 2006
Aeluros has applied for several patents on various aspects of its design implementations of 10G SerDes and PHY functionality. |
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Aeluros Firsts
- 1st 10G PHY with <1W power consumption
- 1st integrated EDC/10G PHY for XAUI-based LRM modules
- 1st production released CMOS-based PHY/ SerDes suitable for X2 and XPAK optical modules applications
- 1st CMOS PHY/SerDes available in Green/RoHS/ lead-free packages
- 1st multi-protocol (LAN/ WAN/FC) 10G PHY capable of operating with a single external clock source
- 1st integrated VCSEL driver/10G PHY
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