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Aeluros Announces Silicon-Proven Intellectual Property Offerings for PCI Express, 3.0 Gbps Serial ATA II, and XAUI Portfolio of silicon-verified IP cores addresses expanding need for high-quality solutions for high-speed serial I/O Mountain View, CA, June 10, 2004 - Aeluros today announced the general availability of silicon-proven physical-layer intellectual property (IP) offerings for PCI Express, 3.0 Gbps Serial ATA (SATA) II, and XAUI. With the implementation of high-speed serial I/O rapidly propagating from its traditional role in the communications market into new applications in computing and storage, the challenge of obtaining and integrating high-quality I/O blocks has become a common problem in semiconductor design. Aeluros’ IP products provide a robust solution for this need, and offer a low-power, small-footprint, high-performance implementation for the silicon IC designer. “The rapid growth of PCI Express and Serial ATA demonstrate computing, storage and consumer industry recognition of the advantages of serial I/O,” said Richard Egan, President and CEO of Aeluros. “However, with these advantages comes the need for a physical layer solution able to overcome the associated challenges of signal integrity and high performance. The Aeluros IP cores provide a natural complement to our 10 Gbps standard product activity, and help provide access to the robust Aeluros high-speed links to a new category of strategic customers.” Aeluros has completed several successful intellectual property engagements to date, and the general release of these cores represents their introduction to widespread availability. As a semiconductor device supplier, Aeluros possesses the detailed understanding and demonstrated ability to conquer design issues relating to volume production of quality I/O cells. PCI Express The 2.5 Gbps PCI Express interface has been widely hailed as the natural successor to the PCI bus as a ubiquitous computing interface. Targeted for integration into PC chipsets by the end of 2004, the number of products integrating PCI Express is rapidly on the rise. While early end product implementations make use of PCI Express-to-legacy PCI bridges, cost requirements have placed native physical layer integrations in high demand. Furthermore the growth of the PHY-compliant Advanced Switching protocol represents further expansion in the need for a PCI Express solution. Aeluros’ PCI Express IP core provides a complete implementation of the physical layer of the PCI Express standard, and offers an industry-standard PHY Interface to the PCI Express architecture (PIPE) connection to a device’s internal digital logic. Configurable in single or dual implementations, and capable of expansion up to a full 32-bit wide implementation, the Aeluros PCI Express core includes full support for the power management settings, multiple loopback paths, beacon signaling, hot plug implementation and receiver detection features of PCI Express. 3.0 Gbps Serial ATA II The 3.0 Gbps 2nd generation SATA II interface provides a backwards-compatible speed upgrade to the widely deployed 1.5 Gbps Serial ATA standard. With 1st generation 1.5 Gbps SATA already in extensive use in desktop applications and integrated into chipset south bridges, the performance boost of 3.0 Gbps SATA II, combined with the deployment of SATA II port multiplier devices, will increase the applicability of SATA to the enterprise market. Physical-layer compatibility with the 3.0 Gbps Serial Attached SCSI (SAS) interface further expands the applicability of the 3.0 Gbps SATA II standard, as enterprise-class storage systems are provided with the flexibility to mix-and-match SAS and SATA hard drives to individually manage cost and reliability tradeoffs. Aeluros’ 3.0 Gbps SATA II IP core provides a complete implementation of the physical layer of the SATA II standard, with a standard parallel interface to higher-level logic. Full support is provided for generation and reception of data modulated with spread spectrum clocking (SSC), providing EMI improvements important for computing and consumer applications. Additional feature support includes adjustable output swing, slumber and partial power saving modes, programmable out-of-band signaling, multiple loopback modes and hot plug support. The IP core also supports both transmit and receive programmable equalization capabilities, facilitating its use in storage backplane applications. XAUI The 3.125 Gbps 10 Gigabit Ethernet XAUI interface and 3.1875 Gbps 10 Gigabit Fibre Channel XAUI interface have seen wide deployment for chip-to-chip and backplane implementations in 10 Gigabit design. The Aeluros XAUI solution has been extensively proven through implementation in the Puma AEL1001 and AEL1002 devices, each providing a 10 Gbps to XAUI physical layer implementation for XENPAK/XPAK/X2 optical modules or to provide a bridge to XFP modules. The XAUI IP core contains integrated pre-emphasis support for transmit equalization and has been demonstrated through extensive interoperability tests to function across up to 40” of standard FR4 material. Process & Availability All three of these Aeluros IP cores have been silicon verified and are available today. These cores are available for TSMC or UMC generic 0.13um process technologies, and feature small footprints and low power requirements. Furthermore, Aeluros IP blocks require a minimal number of metal layers in the design, providing extensive layout routing flexibility. Contact your local Aeluros sales representative for more details on these blocks, or to discuss your individual requirements. About Aeluros Aeluros, Inc. is a fabless semiconductor company innovating serial, high-performance, high-density physical layer (PHY) solutions in mainstream CMOS technology. Led by a technical and business management team with a unique understanding of the intricacies involved in building highly integrated 10 Gbps systems, Aeluros has successfully delivered to the communications and computing markets a series of analog-intensive IC devices and IP cores demonstrating distinct advantages in density, power, performance and cost. For more information about Aeluros, please visit the company’s web site at www.aeluros.com. Editorial Contact: Grant Smith Aeluros, Inc. (650) 917-2016 gsmith@aeluros.com Back to Press Releases/Events  |
COPYRIGHT 2003, AELUROS INC. ALL RIGHTS RESERVED
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