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Aeluros Expands Successful 10 Gbps PHY CMOS IC Family With Introduction of WAN Support Pin-Compatible Low-Power, Low-Cost Puma WIS Variant Available Now Mountain View, California, March, 7, 2005 - Aeluros today announced the immediate availability of the AEL1004 device, a WIS-enabled enhancement to the Puma product family of 10 Gbps-to-XAUI physical layer devices. Built upon the market and technology successes of the Puma AEL1001 and AEL1002 devices, the Puma WIS variant maintains the low power and optimized cost structure made possible by 0.13um CMOS process technology, plastic BGA packaging and expert design techniques, while also achieving SONET-quality jitter performance. With optional LAN-only & SAN-only modes, the Puma WIS AEL1004 device provides an optimal single-chip solution for WAN, LAN, or SAN applications. The WAN Interface Sublayer (WIS) is an enhancement defined by the IEEE 802.3ae standard for Ethernet transmission across SONET/SDH and WDM networks. 10 Gigabit Ethernet XAUI data is framed into SONET-compatible packets within a WIS block, and transmitted across an optical network at the SONET data rate of 9.953 Gbps. This greatly enhances the applicability of 10 Gigabit Ethernet for metro and transport applications designed for the reach and reliability of telecom requirements. “The pin compatible nature of the Aeluros Puma WIS device provides us with an effortless transition to WAN-enabled designs,” said Yasuki Mikamura, Lightwave Development Department Head of Optical Transmission Components Division, Sumitomo Electric Industries Ltd. “By not demanding sacrifices in power or performance, the Puma WIS solution will simplify our development and significantly accelerate our design cycle.” The Puma WIS device provides a set of unique clocking capabilities designed for efficient support of WAN/LAN and SAN operation. These clocking capabilities provide additional cost savings and a reduced solution board footprint, two critical considerations in the constrained environment of modern X2 and XPAK 10 Gbps optical modules and high-density line cards. “The Puma WIS variant will further accelerate the rapid adoption of Puma devices in 10 Gbps optical module and line card applications,” said Stefanos Sidiropoulos, CEO of Aeluros. “As the sole robust CMOS 10 Gbps-to-XAUI solution on the market, Aeluros’ Puma devices have become a critical element in market-driven power- and cost-reduction efforts. WAN support expands the addressable market for Aeluros’ Puma products, bringing the flexibility of Ethernet to bear to SONET/SDH & WDM-based networks.” Puma WIS AEL1004 Device Details The Puma WIS AEL1004 device provides a full implementation of the PMA, WIS, PCS, and PHY XS layers as defined by the IEEE 802.3ae 10 Gigabit Ethernet specification and by the INCITS 10 Gigabit Fibre Channel specification. This enables a physical layer bridge between a 10.3125 Gbps, 9.953 Gbps or 10.51875 Gbps serial data stream and a 4-lane 3.125 Gbps or 3.1875 Gbps XAUI interface, appropriate for implementation within XENPAK/XPAK/X2 MSA-based optical modules or for use as a bridge between XAUI-based ASIC and MAC devices and optical modules using the XFP form-factor. When in LAN mode, the Puma WIS AEL1004 device is fully function-compatible with the Puma device, shipping now in general deployment in optical module and system line card applications, and maintains its industry-best 800mW power consumption. The Puma WIS AEL1004 device is fully IEEE 802.3ae and XENPAK register-set compliant, supports the use of external DOM devices or microcontrollers, and includes integrated PRBS and packet-level test pattern generators and checkers for effective device and module built-in self test (BIST) functions. Designed in the same 144-pin, 13x13mm plastic, wirebond BGA package as the Puma device, the Puma WIS AEL1004 implementation has been proven in silicon-based verifications with system and test environments. About Aeluros Aeluros, Inc. is a fabless semiconductor company innovating serial, high-performance, high-density physical layer (PHY) solutions in mainstream CMOS technology. Led by a technical and business management team with a unique understanding of the intricacies involved in building highly integrated 10 Gbps systems, Aeluros has successfully delivered to the communications and computing markets a series of analog-intensive IC devices and IP cores demonstrating distinct advantages in density, power, performance and cost. For more information about Aeluros, please visit the company’s web site at www.aeluros.com. Editorial Contact: Grant Smith Aeluros, Inc. (650) 917-2016 gsmith@aeluros.com Back to Press Releases/Events  |
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