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PHY/SerDes IP Cores
As a semiconductor supplier, Aeluros is familiar with the full spectrum of issues associated with getting a high performance I/O block integrated into silicon and ramped to production. The Aeluros IP solutions are robust, reliable implementations of these crucial system blocks, and are available today for use in your designs. Aeluros's intellectual property portfolio currently includes:
- Standard PHY implementations of XAUI, SATA-II, PCI-express, and
- Other high-speed, low power I/O’s (backplanes, chip-to-chip and custom applications)
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PCI Express
The Aeluros PCI Express PHY IP Core incorporates the 2.5 Gbps I/O, serializer/deserializer and full PHY Interface for PCI Express (PIPE) parallel interface functions. In addition, an extensive collection of features like power management mode support, multiple loopback paths, beacon signaling, hot plug implementation, and receiver detection are all included.
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Serial ATA II
The Aeluros SATA II IP core provides a full physical layer implementation of the 3.0 Gbps SATA standard. With full backwards compatibility to the 1st generation 1.5 Gbps data rate, the Aeluros SATA IP core can be used to address any current SATA physical layer requirements. The Aeluros SATA block features full support for generation and reception of spread spectrum modulated data up to 8000ppm. This spread spectrum clocking (SSC) support can improve the EMI performance of both computing and consumer applications. Additional features include programmable output swing, support for both slumber and partial power-saving modes, programmable out of band signaling thresholds.
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XAUI
The Aeluros XAUI IP core (implemented and verified in the Puma AEL100x family of products) presents a robust implementation, able to drive 40” of standard FR4 material and 2 connectors, more than enough distance for backplane systems. The incorporation of programmable output swing capabilities and a programmable transmit equalization feature ensures support across extended channels, or even for shorter distances, depending on customer requirements.
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Custom high-speed interfaces
Aeluros has also undertaken several custom high speed serial interface designs, including:
- Clocking designs for graphics processor applications
in 90 nm CMOS
- Flexible multi-rate SerDes for SONET, GbE & SATA FPGA applications
in 130 nm CMOS
- High-speed SerDes interface for memory applications
in 90 nm CMOS
- Parallel multi-gigabit/sec interface for a leading gaming company in 65nm CMOS
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